1. Technical Field
The present invention relates in general to distributing a signal to multiple lines through isolation buffers to prevent signal degradation. More particularly, the present invention relates to a system for connecting a single test signal channel of a wafer test system to multiple test probes to enable testing of integrated circuits (ICs) on a wafer.
2. Related Art
Fanning out a signal to multiple transmission lines, as illustrated in FIG. 1, in many cases requires that the signal arrive at multiple destinations with an equal phase shift. For example to fan out a clock signal, a clock tree is used to distribute the clock signal so that signals arriving on multiple lines are synchronized, or distributed without a phase difference at the line destinations. Typically to assure no phase difference, the multiple transmission lines are laid out to have the same length. In some cases, however, it may be impossible to route the multiple lines so that all are the same length. Further, a fault or line degradation may occur on one of the multiple lines that can create a return signal causing interference and significant attenuation of signals on other lines.
Isolation buffers may be provided in the path of each of the multiple transmission lines, as illustrated in FIG. 2, to reduce the effect of faults. Unfortunately, the isolation buffer circuitry will not only add delay to the signals, but it will typically introduce an arrival delay uncertainty, or effectively create phase differences at the destination of the multiple transmission lines. Circuit construction variations and temperature variations are typical contributors to delay variations from one buffer circuit to another that can prove problematic to synchronous circuits.
Although a clock tree provides one example where a signal should be distributed synchronously, it would be convenient to provide such a distribution in other systems if equal phase delays could be maintained. FIG. 3 shows a simplified block diagram of one such system—a test system for testing ICs on a semiconductor wafer. The test system includes a tester 2 made up of a test controller 4 connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being moved into contact with probes 16 on a probe card 18. Cameras 20 and 22 are shown attached to the prober 10 and the test head 8 to enable precise alignment of the probes 16 with contacts of ICs formed on the wafer 14.
In the test system, test data is generated by the test controller 4 and transmitted through the communication cable 6 to the test head 8. Test results then provided from ICs on the wafer are received by the test head 8 and transmitted to the test controller 4. The test head 8 contains a set of tester channels. Typically test data provided from the test controller 4 is divided into the individual tester channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked to the probes 16 through electrical connections 24.
In most cases each of the probes 16 contacts a single input/output (I/O) terminal or pad on an IC of the wafer 14 being tested. Each tester channel may then either transmit a test signal to an IC input or monitor an IC output, signal to determine whether the IC is behaving as expected in response to its input signals. FIG. 4 shows details where each tester channel is linked to a single probe. In FIG. 4, two signal channel transmission lines 31 and 32 are shown provided to two separate probes 161 and 162 contacting pads on two separate ICs 371 and 372 on the wafer 14. Each of the channel transmission lines 31 and 32 is driven by a respective driver 34 and 35, the drivers 34 and 35 typically being located in the test controller 4. Test data from the channel transmission lines 31 and 32 are distributed through the probe card 18 to the separate probes 161 and 162. Once testing is complete, the wafer is diced up to separate the ICs 371-374.
Since there are usually more I/O pads than available tester channels, a tester can test only a portion of the ICs on the wafer at any one time. Thus, a “prober” holding a wafer must reposition the wafer under the probes several times so that all ICs can be tested. It would be advantageous due to test time savings and prevention of possible wafer damage due to multiple contacts with a test system if all ICs on a wafer could be contacted and tested concurrently without having to reposition the wafer.
One way to reduce the number of tester channels needed to test an entire wafer without repositioning the wafer is to distribute or fan out a single test channel to multiple lines, as generally illustrated in FIG. 1, potentially allowing the same tester channel to provide signals to I/O pads of a large number of ICs on a wafer. Although one channel can be fanned out, with fan out a fault identified in test results provided from one DUT may falsely appear in the test results of another DUT. For example a fault in the contact pad on one DUT which is shorted to ground will short the contact pad on a second DUT to ground, causing the second DUT to falsely test as bad. Further, an open circuit fault on one of the lines will render a wafer connected to the line untestable. Either a short or an open on a line will severely attenuate a test signal provided from the same channel to other lines intended for other DUTs.
One way of preventing a fault at or near any I/O pad from severely attenuating a test signal passing through the interconnect system is to place isolation resistors between the probes and a channel line branch point. The isolation resistors prevent a short to ground on one DUT from pulling the other DUT to ground, and likewise significantly reduce the attenuation resulting from an open circuit on one line. FIG. 7 of U.S. Pat. No. 6,603,323 entitled “Closed-Grid Bus Architecture. For Wafer Interconnect Structure,” describes the use of such isolations resistors. Although reducing the affect of faults, isolation resistors do not completely eliminate the attenuation caused by the faults. Further, with a parasitic capacitance on the lines, adding isolation resistors introduces an RC delay that can adversely affect the rise and fall time of test signals, potentially creating erroneous test results.
Another way to isolate faults without introducing resistor attenuation is to include an isolation buffer between each channel branch point and probe, as generally illustrated in FIG. 2, and as illustrated in more detail for a test system in FIG. 5. In FIG. 5, one transmission line channel 42 from a driver 40 of a tester is fanned out to two bus lines 501 and 502 in the probe card 18 to provide the channel signal to separate probes 421 and 422 for contacting pads on two ICs 371 and 372 (each labeled as a device under test “DUT”). Of course a channel could likewise be fanned out over multiple bus lines to multiple pads on the same IC.
A draw back to isolation buffers, as indicated previously, is that they introduce an uncertain delay into the transmission of test signals from the tester to the DUTs on a wafer. The delay is uncertain because the delay through a buffer can change with changes in temperature and power supply voltage. The signal delay from the tester to DUTs on a wafer can change during performance of a sequence of tests on DUTs of a wafer, creating inaccurate test results.
It would be desirable to distribute a signal to multiple transmission lines and provide isolation from faults without introducing an unequal delay, both for a wafer test system, and other systems that distribute a signal over multiple transmission lines.